1. Field of the Invention
The invention pertains to the field of semiconductor fabrication. More particularly, the invention pertains to methods of crystallizing amorphous silicon film and methods of forming thin film transistor structures incorporating the silicon film formed using solid phase crystallization.
2. Description of Related Art
Polycrystalline silicon (polysilicon) thin film transistor (TFT) arrays are used as backplanes for switching liquid crystal displays (LCDs) and also for driving organic light emitting diode (OLED) displays. For the LCD applications, polysilicon TFTs need to be used instead of more popular amorphous silicon (referred to as a-Si or a-Si:H)) TFTs, when peripheral driving circuit is also made using TFTs, since polysilicon TFTs have about two orders of magnitude higher carrier mobility compared to that for a-Si TFTs. Additionally for higher resolutions LCDs, polysilicon TFTs are preferred over a-Si TFTs. For OLED applications, currently the use of polysilicon TFTs is the only practical way to make reliable displays as instability of a-Si TFTs make long-term OLED operations difficult.
In polysilicon TFTs, the active layer (channel layer of TFTs) is made of polycrystalline silicon. During the fabrication of polysilicon TFTs, the channel layer is usually deposited as a-Si and it is subsequently annealed to convert it to the polycrystalline silicon. This process is referred to as crystallization. The crystallization of a-Si needs to be performed at a thermal budget (temperature/time budget) lower than that which could damage glass substrate used for displays. The most commonly used method for crystallization in the display industry today is excimer laser annealing (ELA), as thermal budgets encountered during the ELA process do not cause damage the glass substrate. Although the ELA process is the most commonly used method, it has several disadvantages. First of all, the ELA process is expensive in terms of cost of equipment, its operation and maintenance. Secondly, since the ELA is performed by scanning a pulsed laser beam, there is a non-uniformity in TFT characteristics resulting from pulse-to-pulse variation of energy of the laser beam. The scanning non-uniformity is visible on an image of a OLED display in the form of scan lines. Additionally there is a high surface roughness for polycrystalline silicon layer formed using ELA. For example, for a 500 A thick a-Si precursor, the root mean square (RMS) roughness value for the resulting polysilicon film after ELA is of the order of 100 angstrom with peak to valley distances of several hundred angstroms. The high value of surface roughness for polysilicon formed by ELA process affects the TFT performance adversely.
The least expensive and the simplest crystallization process for a-Si is thermal annealing and it is known as solid phase crystallization (SPC). However, the thermal budgets needed to crystallize a-Si by SPC are too high to be practical for mass production of TFTs. For example, for a-Si films deposited at about 250° C. by a PECVD method, the annealing time needed to crystallize the films at 600° C. is about 15 hours. Such times are too long for mass production of devices.
The annealing times for crystallization can be reduced exponentially by increasing the temperature. For example, for the same a-Si film mentioned above, the crystallization time at 650° C. is about 80 minutes and at 700° C., it is of the order of 10 minutes. However, the glass substrate used for these TFTs can easily bend at these thermal budgets.
The above thermal budgets are typical but can vary somewhat depending on deposition conditions and type of deposition method (example: PECVD, LPCVD, sputtering) used for a-Si films. For example, for the PECVD case, the crystallization thermal budgets are lower, when a-Si film is deposited at higher temperatures. However, such higher-temperature-deposited a-Si films tend to have pre-existing crystal embryos, which result in higher nucleation density upon annealing, leading to reduced polysilicon grain-size. The reduced Si grain-size lowers the device performance.
In order to reduce thermal budget for crystallization of a-Si, people have deposited certain metals such as Ni, Pd etc. on the a-Si surface and crystallized it by a process called metal induced crystallization (MIC) at thermal budget 100 to 150° C. lower than those needed during SPC (Liu, Kakkad, Fonash, U.S. Pat. No. 5,147,826). This method is very attractive because of its lower thermal budget, but during the annealing, there is an incorporation of the metals or their silicides into the entire silicon layer, which affect the device characteristics adversely, especially the leakage current, which increases significantly for these devices.
It was found that a-Si films heavily doped with p-type or n-type dopants crystallized at significantly reduced thermal budgets. For example, by heavily boron doping a-Si films by incorporating boron during deposition (gas phase doping), the crystallization times at 600° C. can be reduced by an order of magnitude compared to that for undoped film deposited under similar conditions, The reduction in crystallization thermal budgets can also seen for other silicon dopants such as phosphorus. Generally no reduction in crystallization thermal budget can be seen for doping concentration below 1019 cm−3 but a significant reduction in the crystallization thermal budget can be obtained for dopant concentrations 1020 cm−3 and higher.
It is also found that the grain size of the heavily doped silicon film after the crystallization is equal to or larger than that for undoped silicon films crystallized at the same temperature. Thus even though the crystallization times for doped films are smaller, the grain size is not reduced.
Although the heavily doped silicon films can be crystallized in shorter times, they can not be used as channels in TFTs. An undoped or lightly doped film is needed for the channel layer of TFTs.